1. Field of the Invention
The present invention relates to a semiconductor memory device and fabrication method thereof.
2. Background of the Art
An SRAM(Static Random Access Memory) cell, also referred to as a flip-flop, is composed of a pair of cross-coupled inverters. That is, the memory cell""s logic state is determined by a voltage level of each a pair of inverter output nodes, and when an inverter output node to which a supply voltage is applied is at a low voltage level, the other inverter output node maintains a high voltage level. Once the memory cell becomes stabilized, the stable state is maintained, so that a SRAM cell does not require a periodic refresh operation for having data stored therein, and such a characteristic of the SRAM cell is distinguishable from a DRAM (Dynamic Random Access Memory) cell. As a result, an SRAM cell is more stably operated than a DRAM cell, with a less power consumption. Also, due to self-restoring, peripheral circuits characteristics, the SRAM cell is operated in a faster mode, compared to other kinds of semiconductor memory cells.
However, it is known a disadvantage of the SRAM cell that the SRAM cell requires at least 6 transistors for forming a single cell of the kind and accordingly exhibits a lower integration factor.
To solve the above-described disadvantage, there has been proposed a high-resistance load cell for 1 Mbit SRAMs by taking advantage of a polysilicon resistor, which permits a smaller region to be occupied by a memory, cell. Here, because the SRAM cell is provided with a four-transistor set and a polysilicon resistor, it is advantageous compared to a six-transistor SRAM in terms of the chip region occupied thereby. However, in a greater than 4 Mbit SRAM, a six-transistor TFT (Thin Film Transistor) SRAM cell is widely adopted mainly due to a cell data retention stability and reduced current consumption, even though the TFT SRAM cell is composed of a six-transistor set, and further TFT SRAM cell occupies a larger region than a high-resistance load SRAM cell which employs a polysilicon resistor.
With reference to FIG. 1, an equivalent circuit of a conventional SRAM cell is provided with a pair of NMOS access transistors Ta1, Ta2, a pair of NMOS drive transistors Td1, Td2, and a pair of PMOS load transistors Tl1, Tl2, wherein the access transistors Ta1, Ta2 will be referred to as a first and second access transistors, the drive transistors Td1, Td2 will be respectively referred to as the first and second drive transistors, and the load transistors Tl1, Tl2 will be respectively referred to as first and second load transistors or first and second load resistors.
The gates of the first and second access transistors Ta1, Ta2 are respectively connected to a word line. One end of the channel of the first access transistor Ta1 is connected to a bit line BL, and node A connected to the other end of the channel of the first access transistor Ta1 is connected in common to the gate of the second load transistor Tl2 and the gate of the second drive transistor Td2. One end of the channel of the second access transistor Ta2 is connected to a complementary bar bit line /BL, and node B of the second access transistor Ta2 is connected in common to the gate of the first load transistor Tl1 and the gate of the first drive transistor Td1. The source region of each of the first and second load transistors Tl1, Tl2 is connected in common to high level supply voltage Vdd, and the source region of each of the first and second drive transistors Td1, Td2 is connected in common to ground voltage Vss.
The operation of the thusly-constituted SRAM cell will now be described.
First, referring to a write operation of the SRAM, in order to write a data xe2x80x9c1xe2x80x9d in an SRAM cell, when a word line voltage is raised to a level of supply voltage Vdd so as to turn on the first and second access transistors Ta1, Ta2, the high level supply voltage Vdd is applied to the bit line BL, and the low level ground voltage Vss is applied to the bar bit line /BL, then the voltage at node A becomes a value of Vdd-Vth, whereby the second drive transistor Td2 is turned on and the second load transistor Tl2 is turned off. The voltage at node B becomes practically 0V, so that the first load transistor Tl1 becomes turned on and the first drive transistor Td1 is turned off, whereby data xe2x80x9c1xe2x80x9d is transferred to the SRAM cell. So long as current is continuously supplied after a data voltage of the SRAM cell is determined, the first load transistor Tl1 remains turned on so that the supply voltage Vdd is applied via the first load transistor Tl1 to the node A, and the second drive transistor Td2 remains turned on so that the current of node B flows through the second drive transistor Td2 to ground Vss, whereby node A is turned to a high level and node B is turned to a low level so as to maintain the stored data. The steps contrary to those for a data xe2x80x9c1xe2x80x9d are taken for a data xe2x80x9c0xe2x80x9d. That is, the low-level voltage Vss is applied to the bit line BL, and the high level voltage Vdd is applied to the bar bit line /BL, so that the node A maintains a low level and the node B maintains a high level.
A read operation will now be described. Assuming that a data xe2x80x9c1xe2x80x9d is written into the SRAM cell, node A is a high level and node B is a low level. The respective charges of bit line pair BL, /BL for reading data are set at about 3V which is an operation point of a sense amplifier in order equalize the bit line pair BL, /BL with regard to voltage. The word line voltage is raised to the level of supply voltage Vdd, and the first and second access transistors Ta1, Ta2 are turned on so as to select the target SRAM cell for carrying out a reading operation. Then, the voltage of the bit line BL is slightly raised toward the level of Vdd due to the current which flows in through the first load transistor Tl1, and the voltage of the bar bit line /BL flows to ground Vss and is slightly lowered, accordingly. At this time, the potential difference between the bit line BL and the bar bit line /BL is amplified in the sense amplifier (not shown) and transferred to an output buffer (not shown). Here, the reading of the data xe2x80x9c0xe2x80x9d follows steps identical to those for a data xe2x80x9c1xe2x80x9d, wherein the voltage fluctuation of the bit line BL and the bar bit line /BL is reversed compared to the case of a data xe2x80x9c1xe2x80x9d.
Meanwhile, in a TFT SRAM serving as one of the thusly operated SRAM kinds wherein the objective of such TFT SRAM is to increase the integration degree, the first and second drive transistors Td1, Td2 and the first and second access transistors Ta1, Ta2 are respectively formed of a bulk transistor, and because the first and second load transistors Tl1, Tl2 are respectively provided with a structure in which the transistors Tl1, Tl2 are sequentially stacked on the first and second drive transistors Td1, Td2, the TFT SRAM becomes advantageous in that it requires less chip region than a general SRAM.
With reference to FIG. 2 illustrating a plan layout view of a conventional TFT SRAM and to FIGS. 3A-3G showing fabrication sequence cross-sectional views thereof, the structure of the TFT SRAM will now be described.
As shown therein, on a semiconductor substrate 1 there is formed a device isolation region 2a. On the region of the substrate 1 other than the device isolation region 2a are formed the first and second access transistors Ta1, Ta2 and the first and second drive transistors Td1, Td2. That is, on the semiconductor substrate 1 are respectively formed gate electrodes 5a1, 5a2 of the first and second access transistors Ta1, Ta2. In the semiconductor substrate 1 and on each side of the gate electrodes 5a1, 5a2 of the first and second access transistors Ta1, Ta2 there are formed the source region regions 3a1, 3a2 and drain regions 4a1, 4a2, wherein the first access transistor Ta1 includes gate electrode 5a1, source region 3a1, and drain region 4a1, and the second access transistor Ta2 is provided with gate electrode 5a2 connected to the gate electrode 5a1, source region 3a2 and drain region 4a2.
Gate electrodes 5d1, 5d2 of the first and second drive transistors Td1, Td2 are formed on the semiconductor substrate 1. On the semiconductor substrate 1 and adjacent to sides of the gate electrodes 5d1, 5d2 of the first and second drive transistors Td2, Td2 are formed source regions 3d1, 3d2 and drain regions 4d1, 4d2 of the first and second drive transistors Td1, Td2, wherein the first drive transistor Td1 includes the gate electrode 5d1, source region 3d1, and drain region 4d1, and the second drive transistor Td2 is provided with gate electrode 5d2, source region 3d2 and drain region 4d2.
The drain region 4a1 of the first access transistor Ta1 is connected by a butting contact to the gate electrode 5d2 of the second drive transistor Td2. The drain region 4a2 of the second access transistor Ta2 is connected by a butting contact to the gate electrode 5a1 of the first drive transistor Td1, but the respective contact regions thereof are not shown in the drawings.
Using the substrate 1 and the upper surface thereof, a gate electrode 7l1 of the first load transistor Tl1 and a gate electrode 7l2 of the second load transistor Tl2 are formed on the first and second drive transistors Td1, Td2. An active layer 9 of the first and second load transistors is formed on the gate electrodes 7l1, 7l2 of the first and second load transistors Tl1, Tl2. In the active layer 9 are formed source region regions 10l1, 10l2 and drain regions 11l1, 11l2 of the first and second load transistors Tl1, Tl2. The source region regions 10l1, 10l2 of the first and second load transistors Tl1, Tl2 are respectively connected to a Vdd line. The node A as shown in FIG. 1 denoting a contact point between the drain region 3d1 of the first drive transistor Td1 and the drain 11l1 of the first load transistor Tl1 is connected through a first contact hole CT1 and a second contact hole CT2 to the gate electrode 5d2 of the second drive transistor Td2 and the gate electrode 7l2 of the second load transistor Tl2. Also, the node B shown in FIG. 1 denoting a contact point between the drain 3d2 of the second drive transistor Td2 and the drain 11l2 of the second load transistor Tl2 is connected through a third contact hole CT3 and a fourth contact hole CT4 to the gate electrode 5d1 of the first drive transistor Td1 and the gate electrode 7l1 of the first load transistor Tl1.
With reference to FIGS. 3A through 3G illustrating cross-sectional process views taken along line IIIxe2x80x94III in FIG. 2, the fabrication process thusly constituted conventional stack type TFT SRAM cell will now be described.
As shown in FIGS. 2 and 3A, in an upper surface of a p-type semiconductor substrate 1 there are formed device isolation regions 2a and active regions 2b respectively of a gate oxide film 41, wherein the device isolation regions 2a are formed using a LOCOS (LOCal Oxidation on Silicon) method. On the active regions 2b of the gate oxide film 41 is deposited a polysilicon layer which is then patterned for thereby forming the gate electrodes 5a1, 5a2 of the first and second access transistors Ta1, Ta2.
In order to form source regions 3a1, 3a2 and drains 4a1, 4a2 of the first and second access transistor Ta1, Ta2, n-type impurities are ion-implanted into portions of the substrate 1 adjacent to each side of the gate electrode 5a1, 5a2 for thereby forming source regions 3a1, 3a2 and drains 4a1, 4a2 of the first and second access transistors Ta1, Ta2.
As further shown in FIGS. 2 and 3B, a photoresist film 42 is formed on the gate oxide film 41 including the patterned gate electrodes 5a1, 5a2 and patterned so as for predetermined portions of the drains 4a1, 4a2 of the first and second access transistors Ta1, Ta2 to be exposed therethrough using a photo lithographic method.
Next, the gate oxide film 41 portions which are on the substrate 1 portion beneath which are formed the drains 4a1, 4a2 of the first and second access transistors Ta1, Ta2 are moved. Here, the gate oxide film 41 is so thin that it is significantly difficult to etchingly remove the gate oxide film 41 without damaging the adjacent drain regions 4a1, 4a2 and causing defects in the first and second access transistors Ta1, Ta2.
Then, after removing the remaining photoresist film 42, another photoresist film (not shown) is formed instead on the remaining patterns as shown in FIG. 3B. The photo resist film (not shown) portions are formed on regions for forming the drive transistors Td1, Td2, and a polysilicon layer is patterned to form the gate electrodes 5d1, 5d2 of the drive transistors Td1, Td2. On the patterns from which the photoresist film is removed a polysilicon layer is selectively deposited for thereby forming the gate electrodes 5d1, 5d2 of the drive transistors Td1, Td2 as shown in FIG. 3C. In FIG. 3C, for convenience"" sake, the gate electrode 5d2 of the second drive transistor Td2 is illustrated but the gate electrode 5d1 of the first drive transistor Td1 is not illustrated in FIG. 3C.
Impurities are ion-implanted into the semiconductor substrate 1 adjacent to the sides of the gate electrodes 5d1, 5d2 of the first and second drive transistors Td1, Td2 so as to form source regions (not shown) and drain regions (not shown) of the drive transistors Td1, Td2. The remaining photoresist film 42xe2x80x2 is then removed.
With reference to FIGS. 2 and 3D, an SiO2 film serving as a first insulation film 6 is formed with a thickness of 50 100 nm over the thusly formed structure including the gate electrodes 5d1, 5d2 of the first and second drive transistors Td1, Td2 by using a CVD (Chemical Vapor Deposition) process. The contact hole CT3 is formed in a predetermined portion of the gate electrode 5d2 of the second drive transistor Td2, and the contact hole CT1 is formed in a predetermined portion of the gate electrode 5d1 of the first drive transistor Td1.
With further reference to FIG. 3E, a polysilicon layer is formed on the CVD SiO2 film serving as the first insulation film 6 and in the contact holes CT1, CT3 using a LPCVD (Low Pressure Chemical Vapor Deposition) process at a temperature of 630(C. In order to control the threshold voltage Vth of the first and second load transistors Tl1, Tl2, phosphorous impurities are ion-implanted through the poly silicon layer which is then patterned to thereby form gate electrodes 7l1, 7l2 of the first and second load transistors Tl1, Tl2.
Also, as shown in FIG. 3F, a gate oxide film serving as a second insulation film 8 is formed on the gate electrodes 7l1, 7l2 of the first and second load transistors Tl1, Tl2 and the first insulation film, wherein the gate oxide film can be one selected from an SiO2 film using the LPCVD process, a multi-layer film of SiO2/Si3N4, and a TESO film.
As shown in FIG. 3F, on a portion of the gate electrode 7l2 of the second load transistor Tl2 is formed the contact hole CT4 for being connected to the drain 11l1 of the first load transistor Tl1, and on a portion of the gate electrode 7l1 of the first load transistor Tl1 is formed the contact hole CT2 for being connected to the drain region 11l2 of the second load transistor Tl2. Using SiH4 gas, an amorphous silicon layer 9 is formed on the second insulation film 8 and in the contact holes CT2, CT4 with a thickness of less than 40 nm at a temperature of 520 C. by a LPCVD process and patterned. The amorphous silicon layer 9 is annealed at a low temperature in order to be polycrystallized, that is, to be polysiliconized. The low temperature annealing is applied to increase the grains of the polysilicon layer in size; the larger the grains, the better becomes an on/off current characteristic of a transistor. The multi-crystallized polysilicon layer 9 is provided to be used for an active layer and a Vdd line of the first and second load transistors Tl1, Tl2.
Then, as shown in FIG. 3G, a photoresist film is deposited on the active layer 9 and the Vdd line 9 of the first and second load transistors Tl1, Tl2 and patterned by applying an etching so as for only a photo resist film pattern 43a to remain on a channel formation region. Using the patterned photo resist film 43a as a mask, BF2 is ion-implanted with an energy of 25 KeV at a 2-4*1014/cm2 dose, for thereby forming source regions 10l1, 10l2 and drain regions 11l1, 11l2 of the first and second load transistors and a Vdd line.
With the introduction of such a TFT SRAM cell structure in which load transistors are stacked on drive transistors, the region occupied by the transistors has significantly decreased in comparison to a former SRAM cell.
However, with semiconductor devices becoming increasingly more integrated, there has been required an SRAM cell which takes up less area therein for transistors compared to the conventional stack type TFT SRAM cell.
Further, in the conventional stack type TFT SRAM, when a contact is formed to connect a drain of an access transistor and a gate electrode of a drive transistor, there must be carried out a process for removing a gate oxide film on the drain of the access transistor. Here, because the gate oxide film is so thin, the gate oxide film is difficult to remove, thereby repeatability, and the focus has been directed to improvement of the contact process which uses a so-called a butting contact.
Accordingly, it is an object of the present invention to provide a trench type semiconductor memory cell structure and fabrication method thereof for obtaining a higher integration than a stack type semiconductor memory cell.
It is another object of the present invention to provide a trench type semiconductor memory cell structure and fabrication method thereof for enhancing reliability by excluding a butting contact step during a process in which a drain of an access transistor and a gate of a drive transistor are connected to each other.
To achieve the above-described objects, in a semiconductor memory device provided with first and second access transistors, first and second drive transistors, and first and second load resistors, a first cell node having a first terminal of the first access transistor, a gate electrode of the second drive transistor and the first load resistor connected thereto in common, and a second cell node having a first terminal of the second access transistor, a gate electrode of the first drive transistor and the second load resistor connected thereto in common, the semiconductor memory device according to the present invention includes a trench formed in a semiconductor substrate and having at least two walls including a first wall and a second wall, and the first drive transistor and the second drive transistor including a source region and a drain region respectively formed at the first wall and the second wall of the trench, and a gate electrode respectively formed on the first wall and the second wall of the trench.
Further, to achieve the above-described objects, in a semiconductor memory device provided with a first and a second access transistors, first and a second drive transistors, and first and a second load resistors, a first cell node having a first terminal of the first access transistor, a gate electrode of the second drive transistor and the first load resistor connected thereto in common, and a second cell node having a first terminal of the second access transistor, a gate electrode of the first drive transistor and the second load resistor connected thereto in common, the semiconductor memory device according to the present invention includes a trench formed in a semiconductor substrate and having at least two walls including a first wall and a second wall, and the first access transistor and the second transistor respectively including a respective gate electrode formed at the first and the second walls of the trench, and a source region and a drain region respectively formed at the each side of the corresponding gate electrode in the semiconductor substrate.
Still further, to achieve the above-describe objects, in a semiconductor memory device including first and second access transistors, first and second drive transistors, and first and second load resistors, a first cell node having a first terminal of the first access transistor, a gate electrode of the second drive transistor and the first load resistor connected thereto in common, and a second cell node having a first terminal of the second access transistor, a gate electrode of the first drive transistor and the second load resistor connected thereto in common, the semiconductor memory device according to the present invention comprises a semiconductor substrate, a trench formed in the semiconductor substrate and having at least four walls including a first wall, a third wall and a fourth wall, wherein the first drive transistor and the second drive transistor each including a source region, a drain region and a gate electrode are formed at the first wall and the third wall of the trench, respectively, the first access transistor and the second access transistor each including a source region, a drain region and a gate electrode are formed at the second wall the fourth wall of the trench, respectively, and the first load resistor and the second load resistor are formed over an upper surface of the semiconductor substrate corresponding to the first and third walls of the trench, respectively.
Also, to achieve the above-described objects, there is provided a semiconductor memory device fabrication method according to the present invention which includes the steps of preparing a semiconductor substrate, forming a plurality of first impurity regions in the semiconductor substrate for serving as source regions and drain regions of a first access transistor, a second access transistor, a first drive transistor and a second drive transistor, forming an insulation layer on the semiconductor substrate, forming a first contact hole in one of the plurality of the first impurity regions serving as the drain region of the first drive transistor, and forming a second contact hole in another first impurity region serving as the drain region of the second drive transistor, forming a conductive layer on the insulation layer and in the first and the second contact holes, forming a plurality of second impurity regions in a portion of the conductive layer for serving as source region and drain region of a first and second load transistor, patterning the conductive layer, for forming a first active layer of the first load transistor and a second active layer of the second load transistor, forming a trench having at least four walls including a first wall, a second wall, a third wall and a fourth wall, by etching a portion of the first and the second active layers and the semiconductor substrate to a predetermined depth of the first semiconductor substrate, wherein the plurality of first impurity regions are exposed at the four walls of the trench, and the plurality of second impurity regions are respectively exposed at a side surface of the first and the second active layers, forming a first gate oxide film on the first wall of the trench and a side surface of the first active layer, and forming a second gate oxide film on the third wall of the trench and a side surface of the second active layer, forming a first gate electrode common to the first drive transistor and the first load transistor on the first gate oxide film and forming a second gate electrode common the second drive transistor and the second load transistor on the second gate oxide film, forming a third gate oxide film on the second wall and the fourth wall of the trench, and forming a gate electrode of the first and the second access transistors on the third gate oxide film.
To further achieve the above-described objects, there is provided a semiconductor memory device fabrication method according to the present invention which includes the steps of preparing a semiconductor substrate, forming a plurality of impurity regions in the semiconductor substrate for serving as source regions and drain regions of a first access transistor, a second access transistor, a first drive transistor and a second drive transistor, forming an insulation layer on the semiconductor substrate, forming a first contact hole in one of the plurality of first impurity regions serving as a drain region of the first drive transistor, and forming a second contact hole in another first impurity region serving as a drain region of the second drive transistor, forming a conductive layer on the insulation layer and in the first and the second contact holes, forming first and second load resistors by patterning the first conductive layer, forming a trench having at least four walls including a fit wall, a second wall, a third wall and a fourth wall, by etching a portion of the semiconductor substrate to a predetermined depth of the semiconductor substrate, wherein the plurality of first impurity regions are exposed at the four walls of the trench, forming a first gate oxide film on the first wall of the trench, and a forming a second gate oxide film on the third wall of the trench, forming a first gate electrode of the first drive transistor on the first gate oxide film and forming a second gate electrode of the second drive transistor on the second gate oxide film, forming a third gate oxide film on the second wall and the fourth wall of the trench, and forming a gate electrode of the first and the second access transistors on the third gate oxide film.